Conventionally Ethernet switches are provided in networks, such as LANs (Local Area Networks) including a plurality of computer units, each of which is associated with a respective MAC address. A data switch such as an Ethernet switch includes a plurality of ingress/egress ports and a switching fabric between them. Data packets arriving at one of the ports have a header containing the MAC address of the computer unit which transmitted the data packet and the MAC address of the destination of the data packet. The Ethernet switch gradually learns associations between incoming MAC addresses and ports, so that it can transmit the data packet to the port corresponding to the destination MAC address.
According to what data packets arrive at a switch, a data packet arriving at a given port may be queued until it can be transmitted. For this reason, the ports each include one or more queues for storing packets. The buffers for different ones of the ports are typically implemented in a single memory device, which may be a RAM memory.
This situation is illustrated in FIG. 1, which shows a shared memory 1 for storing data packets, in one or more queues for each of multiple ports. The packets stored may be identical to the data packets received at the switch, or they may be modified, e.g. with a different header. The memory 1 is structured to include sixteen packet buffers, labeled PB1, . . . PB16. Typically the number of packet buffers is much higher than this. Each of the packet buffers has the same size, referred to here as the PB length. Typically, this may be 256 bytes or 512 bytes.
Suppose that four packets of differing lengths are transmitted successively to the switch. These packets are illustrated schematically in FIG. 2 as packets 5,7,9,11, with each packet being shown with a different respective hashing scheme. The horizontal axis of FIG. 2 labels the lengths of the packets 5, 7, 9, 11 in units of the PB length.
Conventionally, these packets will be stored in the memory 1 as illustrated in FIG. 3, where the hashing corresponds to FIG. 2 to indicate which of the packets are stored in which of the packet buffers. The first packet, packet 5, for example, which is slightly less than twice the PB length, is stored in PB1 and part of PB2. The second packet, packet 7, which is just more than one PB length, is stored in PB3 and part of PB 4. Note that, a given packet buffer does not store data from more than one packet. This means that the memory utilization is not efficient, and resources are wasted, and the performance of the switch can be degraded. For example, if a packet is only 4 bytes longer than twice the PB length, then three whole packet buffers will be required to store it. If the switch runs out of memory 1, the switch may have to refuse to accept new ones which reach it, and packets may be lost.
It is known to address this problem by attempting to optimise the sizes of the packet buffers, but these techniques are only successful to a limited degree, since certain of the packets may use these resources inefficiently.